UPDATED. 2024-07-17 07:31 (수)
'Glass substrates to replace 2.5D package in chips in the future'
'Glass substrates to replace 2.5D package in chips in the future'
  • Noh Tae Min 기자
  • 승인 2024.06.11 19:20
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According to Georgia Tech professor Yong-Won Lee
Image: Georgia Tech
Image: Georgia Tech

The commercialization of glass substrates will threaten the dominance of advanced packaging technology currently in use such as chip-on-wafer-on-substrate (CoWoS) of TSMC, according a university professor.

Glass substrates’ target market was clear and they will be used in AI and server semiconductors in the high-end segment of the chip market, Georgia Institute of Technology professor Yong-Won Lee, whose expertise is advanced packaging, said during an industrial conference in Seoul on Tuesday.

CoWoS is TSMC’s 2.5D package technology where chip dies such as CPU, GPU, I/O, HBM, and others are stacked vertically on an interposer. Nvidia’s A100 and H100 as well as Intel’s Gaudi  is made using this technology.

Glass substrates are being touted as the future of package substrates that will replace the currently widely used flip-chip ball grid array (FC-BGA).

The core of substrate is replaced with glass from resin, which gives it an advantage in surface detachment and uniformity in the alignment of the interconnect and die.

A glass substrate is also expected to introduce package substrates that are over 100x100mm in size, which will allow more chips to be packaged.

Companies researching the technology include Intel, Absolics, Samsung Electro-Mechanics, Dai Nippon Porting, and Ibiden. 

Absolics, a joint venture between SKC and Applied Materials, recently started trial runs at its factory in Georgia with the aim to start commercial production next year.

A glass substrate can mount SoCs and high-bandwidth memory (HBM) chips without the need for an interposer, unlike CoWoS, Lee said. This means more chips can be mounted at a lower height/

George Tech recently showcased its paper that mounted 60 chips (six units of xPU6, 54 units of HBM) on a glass substrate at the 2024 IEEE 74th Electronic Components and Technology Conference held in Colorado last month. This means it had 3.7 times more chip compared to TSMC’s CoWoS-R technology that was also showcased at the conference. 

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