UPDATED. 2024-07-17 07:31 (수)
Samsung and SK Hynix to apply hybrid bonding on 3D DRAM
Samsung and SK Hynix to apply hybrid bonding on 3D DRAM
  • Noh Tae Min 기자
  • 승인 2024.06.18 18:50
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Image: TheElec
Image: TheElec

South Korean memory chipmakers Samsung and SK Hynix are expected to spply hybrid bonding in their upcoming 3D DRAM.

SK Hynix said during the International Memory Workshop 2024 conference held in Seoul last week that it will apply wafer bonding in its 3D DRAM production.

Wafer bonding is also called hybrid bonding, where chips are vertically stacked and connected through through-silicon-via (TSV), or microscopic copper wires, and the I/O are attached directly without bumps.

Depending on how the dies are stacked, they are called wafer-to-wafer, wafer-to-die, and die-to-die.

3D DRAM is a future concept for DRAMs where DRAM cells are stacked vertically like how NAND cells are stacked vertically today.

Samsung and SK Hynix are planning to manufacture the cells and peripherals on different wafers and connect them through hybrid bonding.

This needs to be done as attaching the peripherals on the sides of the cell layers on the same wafer like existing DRAMs expands the surface area too much.

Separating the peripherals on a different wafer makes it convenient to increase the cell density.

Samsung is also researching 4F Square DRAM and is also expected to apply hybrid bonding in their production.

The peripheral wafer will be attached at the bottom and two memory cell wafers will be stacked on top of them. The uppermost memory cell wafer will also have the I/O pad and multilevel metal wiring.

4F Square is a cell array structure that reduces the dies surface area by 30% compared to the 6F Square DRAM currently commercialized.

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