UPDATED. 2024-07-12 07:53 (금)
Jusung developing ALD tech to reduce EUV process steps
Jusung developing ALD tech to reduce EUV process steps
  • Noh Tae Min
  • 승인 2024.07.09 00:54
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Chips to stack transistors in future, chairman says
Jusung Engineering chairman Chul Joo Hwang Image: TheElec
Jusung Engineering chairman Chul Joo Hwang Image: TheElec

Semiconductors going forward will stack transistors on top of each other, Jusung Engineering chairman Chul Joo Hwang said.

This is because scaling DRAM and logic chips are reaching their limits so DRAM and logic chips will, like NAND, stack transistors on top of each other to overcome this, the chairman said.

Hwang claimed this meant that more atomic layer deposition (ALD) technology would be developed that reduces the use of extreme ultraviolet (EUV) process steps during advanced chip production. EUV is a lithography technology developed and supplied by ASML of the Netherlands.

This is because stacking transistors will reduce the need to scale the transistors down to smaller sizes. A supporting fact to this is that deep ultraviolet (DUV) equipment are expected to be used in 3D DRAM production.

As stacking becomes more important, ALD machines will also see a demand increase, Hwang said. III-V and IGZO semiconductors also require ALD machines in their production.


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