UPDATED. 2024-06-14 08:17 (금)
Samsung forms team to develop 4F2 DRAM for under 10nm
Samsung forms team to develop 4F2 DRAM for under 10nm
  • JY Han
  • 승인 2023.05.26 11:28
  • 댓글 0
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Unlike SK Hynix and Micron going 3D DRAM
SK Hynix's 6F2 structure Image: Techinsights
SK Hynix's 6F2 structure Image: Techinsights

Samsung has formed a team to develop a 4F2(feature square) DRAM, TheElec has learned.

If the tech giant succeeds, it will be able to reduce the surface of die by 30% compared to 6F2 DRAM, sources said.

Memory chipmakers attempted to commercialize 4F2 ten years ago but failed at the time.

But now Samsung believes the structure is more achievable compared to 3D DRAM  being developed by rivals SK Hynix and Micron.

Samsung is aiming to start applying the 4F2 structure for DRAM made with 10-nanometer (nm) or under nodes as it believes how much it can narrow the channel length from then on will be limited.

A DRAM consists of billions of cells made out of transistors and capacitors aligned in a square array.

A transistor has a source, gate and drain depending on where the current flows in and out.

The capacitor that stores the charge to determine 1 or 0 is above the drain. The word line and bit line are connected to the gate and source, respectively. The word line handles the switching (on/off) and bit line reads and writes the data.

8F2 was called as such because the structure had four feature(F, or critical dimension)s horizontally by two features vertically, for bit line length and word line length, respectively. 

6F2 was developed by filling the empty spaces of 8F2. It positioned transistors diagonally to reduce the interruption by the bit line. While it was called 6F2, it was more like 7.8F2 (word line with dimensions of 2.6F, bit line with dimensions of 3.0F).

Samsung’s 4F2 aims to have the transistor vertically upwards. From bottom to top it wants to place the source, gate, dram and capacitor. Connecting the word line and bit line will make their dimensions 2F and 4F, respectively. It will be an entirely new structure.

Samsung recently launched its 12nm DRAM, but the real channel length is more like 12.8nm. This is the same for SK Hynix; while Micron’s 12nm is in fact 13.3nm. Samsung aimed for 12.3nm but failed and decided on 12.8nm. All three memory chipmakers are aiming to develop 1nm (1c) and 10nm (1a) next, before going under 10nm.

Under 10nm, Samsung will launch one generation with 4F2; the following generation will use direct bonding to make 2 layers.


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