S&S Tech was currently focusing on improving the defects on its blank mask for extreme ultraviolet (EUV) process in wafer fabrication, TheElec has learned.
Blank masks are used to make the pattern masks to draw circuit designs on the wafer during the EUV lithography process.
Molybdenum-silicon (Mo-Si) are stacked in nanometer (nm) layers on top of the mask. A tantalum alloy is then coated on it to complete the pattern mask.
Besides the blank mask, S&S Tech is also developing a high-k mask to better absorb EUV and a phase shift mask to prevent the light shot down on them from distorting.
The South Korean company is aiming to mass-produce these masks in 2024.
S&S Tech has so far successfully reduced the potential defects, such as particles, this year and is planning to adopt new inspection equipment to reduce them further next year.
Blank masks for EUV require more precise checks for defects compared to argon fluoride to the shorter wavelength of the light.
Current blank masks require no defects over 60nm in size __ for masks in EUV, this needs to be reduced to 30nm.
S&S Tech has succeeded in reducing the number of defects to under a hundred.
It is planning to use inspection of the multi-layer of Mo-Si through a third party in Japan.